Reducing power consumption of circuits and systems continues to be a difficult but necessary task particularly for circuits used in mobile devices such as laptop devices, handheld devices and other mobile and non-mobile devices. In addition, advances in technology create an increased demand for power consumption in order implement performance improvements afforded by the advances in technology. In many instances, the performance needs of applications implemented by the circuits are variable depending on the context of the application.
For example, when a synchronous dynamic access memory (SDRAM) circuit is not being accessed (e.g., read/write access), the SDRAM circuit can operate in a self-refresh mode. When in the self-refresh mode, the SDRAM circuit uses it own timer to generate internal refresh cycles. As such, a memory controller associated with the SDRAM circuit does not need to provide a clock signal to the SDRAM circuit and therefore can power down memory controller circuits that provide the clock signal when the SDRAM circuit is in the self-refresh mode.
However, some memory controller circuits cannot be powered down when the SDRAM circuit is in the self-fresh mode. The JEDEC Standard (JESD79C), which is hereby incorporated by reference in its entirety, requires a clock enable signal (CKE) to be provided to the SDRAM circuit when it is in both the self-fresh mode and a normal mode of operation. More specifically, the JEDEC Standard requires the clock enable signal to be a logical low while the SDRAM circuit is in the self-refresh mode. When the clock enable signal transitions to a logical high, the SDRAM circuit exits the self-refresh mode and enters the normal mode of operation.
Accordingly, a need exists for a circuit and method to further reduce power consumption in connection with SDRAM circuits while complying with the JEDEC standard.